Non-volatile memory devices are used in any application that where the storage of information is to be maintained even when the memory devices are not powered. In recent years, the market of non-volatile integrated memories (or embedded Non-Volatile Memory—emNVM) has undergone considerable development. The emNVM are implemented with other devices on a single chip to obtain (electronic) systems on chip (System-on-Chip—SoC). The emNVM are implemented in the SoC, for example, to allow post-production calibration/adjustment (e.g., for analog and/or radio-frequency circuits) by the manufacturer and/or post-production customization/configuration by the final user. Moreover, the NVM are implemented in a SoC that for storing a limited amount of data in systems such as radio frequency identification (RFID).
Several technological approaches are available to create an emNVM. Some approaches allow a single programming (one time programmable) of the emNVM, such as poly-fuse or anti-fuse emNVM types.
Other technological approaches allow performing more write cycles of the emNVM, such as in the case of EEPROM (Electrical Erasable and Programmable Read-Only Memory) or FLASH emNVM, which store a datum by trapping electric charges in an insulated, or floating (floating gate), terminal of a storage transistor. However, such types of memory cells use technologies and processes that may not be included in standard CMOS (e.g., to provide the floating gate transistors) usually used to implement a SoC. In fact, the storage transistors have an additional polysilicon layer to define regions of their floating gates (in addition to that used to define their control gate regions as in the standard CMOS). This difference adds design complexity, which significantly increases the manufacturing cost of memory devices.
In the art, floating gate type memory cells obtainable using standard CMOS processes have been developed. For example, single-poly EEPROM (or single polysilicon EEPROM) were developed, which may be implemented in standard CMOS technology because they use only polysilicon one level.
In such memory cells the floating gate is made from a single layer of polysilicon shared between a control capacitor, which dominates and controls the potential of the gate terminal of a MOS transistor connected thereto by means of capacitive coupling. The programming and erasing of the cell may occur by hot carrier injection (HCl), such as channel hot electron (CHE), or for Fowler-Nordheim (FN) tunneling in the floating gate in proximity of the drain region of the floating gate transistor. Italian Patent Application No. MI2009A002349 by the Applicant of the present application discloses an emNVM that implements memory cells of single-poly type.
In addition to the more common mechanisms of FN tunneling injection and CHE, another mechanism includes band-to-band tunneling-induced hot electron (BBHE) for the programming operation in single-poly EEPROM. U.S. Pat. Nos. 5,940,324 and 5,761,126 disclose examples of memory cells programmed by BBHE generated corresponding to the drain region of a MOS transistor of the memory cell.
Such memory cells include rather complex (and of considerable size on the chip) control circuitry (e.g., row and column decoders, reading and writing unit, etc.) because they generate and provide to each cell in a matrix of the emNVM, a plurality of different voltages, also of high value (compared with a supply voltage of the SoC in which the emNVM is integrated).